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vishay siliconix sip11203/sip11204 document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 1 work-in-progress synchronous rectifier driver with power up/down control, output ovp, error amplifier and precision reference features ? high current synchronous rectifier drivers - 2.2 a source and 4 a sink ? driver switching syn chronized with primary controller ? full output control during power-up and power- down ? 5.5 v to 13 v operating voltage range ? 1.225 v on board bandgap voltage reference ? can be powered from the pulse transformer supply- ing synchronous rectifier timing signals ? on-chip ground-sensing error amplifier ? programmable rising edge delay ? output over-voltage protection (ovp) - sip11203 turns synchronous rectifiers on - sip11204 turns synchronous rectifiers off ? secondary-side companion chip for the si9122 half-bridge controller ic applications ? high efficiency dc-dc converter modules and bricks ? telecom and server power supplies ? high efficiency intermediate bus converters (ibc) ? half-bridge, full-bridge, or push-pull primary dc-dc topologies ? center-tapped or current-doubler secondary con- figurations description the sip11203/sip11204 provide the secondary side error amplifier, reference voltage and synchronous rectifier drivers for isolated converter topologies. both ics are capable of being powered via conventional bias supplies (output inductor winding or power trans- former winding), or from a pulse transformer supplying the gate timing signals, and both parts generate a reg- ulated supply for powering the error amplifier and con- trol circuitry. during power-up the sip11203/sip11204 ensure that the synchronous rectifiers are held off until the supply voltages are adequate to guarantee effective opera- tion of the driver circuits. during the soft-start interval, a gradual ramp-up of the synchronous rectifier con- duction time is provided. both ics also allow control of the discharge rate of the synchronous rectifier driver outputs during power-down. the sip11203 and sip11204 are available in a pb-free mlp44-16 package and are rated to handle the industrial ambient temperature range of - 40 to 85 c. typical application circuit out b out a v in i n a i n b o v pin ea+ v lcpd rdelrpd g n d v ref ea- eao u t pg n d half brid g e sip11203 sip11204 v i n g n d v out g n d pwm controlle r optoisolator p u lse transformer zf1 zf2 srh srl
www.vishay.com 2 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 notes: a. device mounted with all leads soldered to printed circuit board. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit v in , in a , in b 15 v v ref , linear inputs - 0.3 v to v l + 0.3 v storage temperature - 65 to + 160 c junction temperature - 40 to +125 package thermal impedance (r ja ) 16 pin 44mlp 47 c/ w package power dissipation (package) a 745 m w recommended operating range parameter limit unit v in 5.5 to 13 v c vin 1 f c vl 1 c ref 0.1 linear inputs (ea+, ea-, ovp in ) 0 to v l error amplifier output voltage 0 to 3.5 v logic inputs (in a , in b ) 0 to 13 reference voltage output current 10 a r pd > 15 k c pd 1 to 10 nf specifications parameter symbol test conditions unless otherwise specified 5.5 v v in 13 v t a = - 40 to 85 c limits unit min a typ b max a power supply v l output voltage v l output disabled (note e) 4.75 5.0 5.25 v v l temperature coefficient tc1 (note c) 160 v/c v l line regulation v l_lnr i l = 0 ma 38 mv v l load regulation v l_ldr i l = 0 ma to 3.3 ma, v in = 5.5 v 1.2 10 v l supply psrr v l_psrr f test =100 hz, (note c) 70 db supply current i in v in = 5.5 v, c load(a) = c load(b) = 6 nf (note c, d) 12 ma v in = 7.5 v, c load(a) = c load(b) = 6 nf (note c, d) 15.5 quiescent current i q device switching disabled (note e) 3.5 4.5 start-up current capability i startup current sourced from v in to v l , v l = 0 v 35 45 55 reference voltages v ref voltage v ref i ref2 = 0 ma, t a = 25 c 1.212 1.225 1.238 v i ref2 = 0 ma 1.188 1.225 1.262 v ref temperature coefficient tc2 (note c) 160 v/c v ref load regulation v ref_ldr v in = 5.5 v, i ref = 0 to 10 a 1.5 2.5 mv v ref psrr v ref_psrr f test = 100 hz, (note c) 60 db internal buffered reference voltage v refint v in = 5.5 v, measured at r pd pin 2.320 2.5 2.570 v
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 3 vishay siliconix sip11203/sip11204 parameter symbol test conditions unless otherwise specified 5.5 v v in 13 v t a = - 40 to 85 c limits unit min a typ b max a logic inputs - in a and in b input high v ih rising 4.0 2.5 v input low v il falling 2.1 1.0 input resistance r in v in = 13 v, 13 v at ina and/or inb 3.0 3.8 4.5 k input frequency range (ina and inb) f in (note c) 100 500 khz error amplifier - dc electrical characteristics voltage gain a v 20 log ( v out / v os ) for v out = 0.5 v to 3.0 v 65 70 db common mode rejection ratio cmrr input cmr = 0 v to 3.5 v 60 65 input offset voltage v os v cm = 1.225 v, r load = 10 k to v cm 3 15 mv v os temperature coefficient tc3 (note c) 30 v/c input bias current i bias v cm = 1.225 v 210 na input offset current i os (i ea+ ) - (i ea- ), (note c) 0.3 output voltage v ol output sinking 0.8 ma 225 400 mv v oh output sourcing 0.8 ma 3.0 3.45 v output current i oh sourcing, ea out = 1.0 v, ea+ overdrive = 500 mv 3.5 4.7 ma i ol sinking, ea out = 2.5 v, ea+ overdrive = 500 mv 0.8 1.3 error amplifier - ac electrical characteristics gain-bandwidth product b w (note c) 1 mhz slew rate sr+ rising, r load = 2 k ii 1 nf to ground 0.75 v/s sr- falling, r load = 2 k ii 1 nf to ground 1 mosfet drivers driver impedance r d(source) v in = 5.5 v, i out = 100 ma, t j = 25 c 2.3 3.7 r d(sink) 1.5 2.4 r d(source) v in = 7.5 v, i out = 100 ma, t j = 25 c 2.1 3.4 r d(sink) 1.4 2.2 peak drive current i pk(source) v in = 5.5 v, t j = 25 c (note c) 1.2 a i pk(sink) 2.4 i pk(source) v in = 7.5 v, t j = 25 c (note c) 2.2 i pk(sink) 4.0 rise time t r 10 % to 90 %, v in = 5.5 v, c load = 6 nf, (note c) 45 ns 10 % to 90 %, v in = 7.5 v, c load = 6 nf, (note c) 42 fall time t f 90 % to 10 %, v in = 5.5 v, c load = 6 nf, (note c) 35 90 % to 10 %, v in = 7.5 v, c load = 6 nf, (note c) 32 in to out propagation delay t pdr ina/inb rising to outa/outb rising, 50 % to 50 % v in = 5.5 v, r del connected to v l , c load = 0 nf 20 32 55 t pdf ina/inb falling to outa/outb falling, 50 % to 50 % v in = 5.5 v, r del connected to v l , c load = 0 nf 20 34 55 additional rising edge out a/b delay vs. r del t delay r del connected to v l 0 r del = 25 k to gnd, c load = 0 nf (note d) 28 38 48 power-down detection timeout t pddet in a and in b low to out a/out b low r pd = 25 k , c pd = 1 nf (note c) 25 s power-up output hold-off current i hoff no forcing voltage on v in or v l , both v in and v l bypassed by 1 f to gnd, ina or inb = 5 v, other input = 0 v, force 1 v at active output (a or b) 350 530 ma specifications
www.vishay.com 4 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 notes: a. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum and over - 40 c to 85 c. b. typical values are specified for 25 c operation, and are for design reference only. c. not 100 % tested in production. this info rmation is provided for reference only. d. in a or in b switching at 250 khz, r del = 25 k to ground. e. in a = step 5 to 0 v and in b = 5 v or vice versa, r del = 25 k to ground, error amplifier configured as voltage follower with ea+ connected to v ref. pin configuration parameter symbol test conditions unless otherwise specified 5.5 v v in 13 v t a = - 40 to 85 c limits unit min a typ b max a under voltage lockout section uvlo threshold (rising) uvlo r v in rising until output transitions on 4.3 4.45 4.6 v uvlo threshold (falling) uvlo f v in falling until output transitions off 2.9 3.05 3.2 uvlo hysteresis v hys(uvlo) uvlo r - uvlo f , i l = 0 ma 1.25 1.40 1.55 output overvoltage protection force outputs on threshold ovp r rising voltage on ovp in to force outa and outb high 1.40 1.47 1.55 v resume normal operation threshold ovp f falling voltage on ovp in to allow outa and outb to go low 1.06 1.13 1.20 hysteresis v hys(ovp) ovp r - ovp f 0.30 0.35 0.40 housekeeping supply section ic logic enable cuvlo r v in rising until current at v in > 1 ma 3.35 3.55 3.70 v ic logic disable cuvlo f v in falling until current at v in < 0.25 ma 2.90 3.05 3.20 hysteresis v hys(cuvlo) cuvlo r - cuvlo f 0.35 0.50 0.65 specifications top v ie w bottom v ie w mlp44-16 outb r pd c pd v ref o v p i n ea ea- ea+ out outa g n dr v del l i n b v pg n d i n a i n outb r pd c pd v ref i n b v i n a i n pg n d o v p i n ea ea- ea+ out outa g n d r v del l 13 14 15 16 1 2 3 4 567 8 9 10 11 12 1 2 3 4 9 10 11 12 13 14 15 16 5 6 7 8 ordering information part number marking ambient temperature range SI11203DLP-T1-E3 11203 - 40 to 85 c si11204dlp-t1-e3 11204
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 5 vishay siliconix sip11203/sip11204 functional block diagram pin description pin number name function 1 inb logic input for output driver b 2 v in input supply voltage 3 pgnd power ground 4 ina logic input for output driver a 5 outa driver output a 6 gnd analog ground (connect gnd to the exposed pad of the ic package) 7 r del sets output rising edge delay 8 v l 5 v supply voltage for internal circuitry 9 ea out error amplifier output 10 ea- error amplifier inverting input 11 ea+ error amplifier non inverting input 12 ovp in input pin for over voltage detection 13 v ref 1.225 v reference voltage for converter output voltage regulating setting 14 c pd capacitor value sets power down det ection time in conjunction with r pd 15 r pd resistor value sets currents for power down det ection timer and for power down discharge of outputs 16 outb driver output b figure 1. 5 v pre-regulator
www.vishay.com 6 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 detailed operation supply voltage (v in ) the sip11203/11204 are designed to operate at an input voltage (v in ) between 5.5 v and 13 v. the syn- chronous rectifier drivers (outa and outb) are pow- ered directly from v in , to facilitate setting the gate drive voltage for the rectifier mosfets. due to the high peak currents available from the sip11203/sip11204 outputs, careful attention must be paid to the bypass- ing of v in to pgnd. internal supply (v l ) in order to provide the internal circuitry of the sip11203/sip11204 with a stable supply voltage (v l ), the sip11203/11204 incorporate a linear pre-regula- tor. operating from v in , the pre-regulator provides a fixed v l of 5 v for use by the majority of the chip. v l is regulated by v refint , and therefore does not depend upon the voltage at the v ref pin. for proper ic opera- tion, a bypass capacitor on the order of 1f should be connected between v l and gnd. in normal operation, v l is intended to accommodate the internal light load requirements, such as bias net- works and the sourcing capa bility of the error ampli- fier?s output. start-up considerations the average pre-regulator output current available to charge the v l bypass capacitor, and the value of that capacitor, play an important part in the start-up sequencing of the sip11203/sip11204. until v l reaches the chip undervoltage lockout threshold (cuvlo), the part is held in a low-current standby state. w hen v l exceeds the cuvlo voltage of 3.55 v, the majority of the on-chip circuitry is enabled, with the exception of the reference voltage buffer and the out- put drivers (outa and outb). finally, when the main undervoltage lockout threshold (uvlo r ) is reached, which occurs when v l reaches 90 % of its final value, the v ref buffer and the output drivers are enabled. this in turn allows the v ref pin to source current, and the outputs to respond to the ina and inb inputs. see figure 4, in the applicat ions information section. the i-v characteristic of the pre-regulator approximates that of a constant current source. w ith v in = 7.5 v , the typical i out at the v l pin for voltages between 0 v and the final regulated voltage of 5 v is 35 ma. reference voltage (v ref ) the sip11203/sip11204 incorporate an internal volt- age reference of 2.5 v. this is scaled and buffered to drive the v ref pin at 1.225 v. the accuracy of v ref is 1 % at 25 c, with a temperature coefficient of 160 v/c, yielding a worst-case accuracy over tem- perature of 3 % (- 40 c to + 85 c). start-up and soft-start considerations v ref is held at 0 v until v l has exceeded its uvlo r threshold. this allows a soft-start function to be imple- mented by controlling the rate of rise of voltage on the v ref pin, which in turn causes a gradual rise in the target voltage of the error amplifier and its associated voltage control loop. see figure 4, in the applications information section. the charging rate (dv/dt) of v ref is user-settable by choice of v ref bypass capacitor value. the i-v char- acteristic of the reference output approximates that of a constant current source, with the typical i out at the v ref pin for voltages between 0 v and the final regu- lated voltage of 1.225 v being 410 a. see the graph ?v ref start-up.? error amplifier the error amplifier is biased from the internal 5 v sup- ply (v l ). the input common mode range extends down to ground and up to 3.5 v. the output stage can source in excess of 4 ma and can sink 1 ma. the output stage is comprised of a class-a source follower working into a 1 ma pull down (current sink), and is designed to drive light loads such as an optocoupler and the series resistor. the output source current i oh is limited by an internal 500 resistor, to protect the output in the event of a short to gnd. w hen sourcing current in excess of 1 ma, the voltage drop across this resistor should be taken into account (see graph of v oh vs. i load ). the 1 mhz amplifier has 75 degrees of phase margin, and a large signal slew rate is (1 v/s) in a uni- tygain configuration. the input offset voltage is typi- cally 3 mv at 25 c, and the offset voltage temperature coefficient is typically 30 uv/c. due to its cmos inputs, the amplifier has low input bias and offset cur- rents. both amplifier inputs as well as the output are accessible, to facilitate meeting the compensation requirements of specific applications. note that the error amplifier output is clamped low until the v l volt- age has increased past the cuvlo r voltage level.
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 7 vishay siliconix sip11203/sip11204 mosfet rectifier drivers start-up at converter start-up, v l will typically be at or near 0 v. until such time as the uvlo r threshold is exceeded, the main synchronous rectifier drivers are disabled, as the supply voltage for the ic may be insufficient to ensure that the output driver s will fully respond to input commands. w ithout precautionary measures, capaci- tive coupling between the drains and gates of the syn- chronous rectifiers could cause spurious conduction in the rectifiers. to prevent this, special hold-off mos- fets are switched in until the main drivers are enabled. these internal hold-off mosfets, which connect from outa to pgnd and outb to pgnd, can typically conduct in excess of 400 ma with 1 v on outa or outb (z out ? 2.5 ). once v l rises above uvlo r , the main drivers are enabled and the part assumes its normal mode of operation, with pulses at ina being used to control outa and pulses at inb being used to control outb. figure 3 and its related text provide additional details on this topic. normal operation w hen enabled, the main driver outputs are non-invert- ing with respect to the input signal. the drivers are designed to provide the high peak currents (2 - 4 a) required to rapidly charge and discharge the gates of large synchronous rectifier mosfets, with a greater turn-off (pull-down) current than turn-on (pull-up) cur- rent, to prevent shoot-through in the synchronous rec- tifiers. shut-down in the typical application circuit, cessation of primary timing signals at ina and inb would cause both outa and outb to be pulled high, which at the system level would short-circuit of the converter output to ground via the synchronous rectifiers. to avoid possible neg- ative effects of such an event, the sip11203/sip11204 uses a missing-pulses detector to monitor ina and inb and, if necessary, set the main output drivers to a high- impedance state. at the same time that the main driv- ers are disabled, a pull-down device (current sink) of user-settable value is enabled on each output, to grad- ually discharge outa and outb, thereby performing a soft turn-off of the rect ifier mosfets. the pull-down current is set by the r pd resistor, and is given by the formula i pull-do w n = 500 v/r pd . such an event also causes bypass capa citor at the the v ref pin to be dis- charged, preparing the ic for a voltage-loop soft-start should the primary resume sending timing signals. further details are given in the applications informa- tion section. synchronous rectifier phase-in w ith a resistor connected between the r del pin and ground, the sip112 03/sip11204 will increase the low- to-high propagation delay time from ina and inb to outa and outb by an amount t del . this interval is proportional to the resistance used, and inversely proportional to the voltage on v ref ( t del = k x r del / v ref ). as this delay occurs for high-going input transi- tions only, it constitutes a hold-off time for the synchro- nous rectifiers. as can be seen, t del decreases as v ref ramps from a low level to its final 1.225 v level at start-up, or following any soft-start event. if t del is set to start at a sufficient value to allow only diode- mode conduction in the rect ifier mosfets, the result will be a gentle transition fr om diode-mode operation to fully synchronous rectification, thereby avoiding a sud- den change in the average voltage drop seen at the output rectifiers. conventional operation can be achieved by tying the r del pin to v l . the synchronous rectifier phase-in function is explained in more detail in the applications information section. output over-voltage protection: sip11203 versus sip11204 for maximum flexibility in th e way that the sip11203/ sip11204 parts react to an output over-voltage event, the input to the over-voltage protect comparator (ovp in ) is brought out separately from the error ampli- fier inputs. additionally, the outputs of the sip11203 and the sip11204 respond differently to an over- voltage : the sip11203 is designed to rapidly dis- charge an output bus that is experiencing an over-volt- age, while the sip11204 is designed to avoid sinking current from other supplies feeding the same bus, rely- ing instead upon system-level intervention to provide complete load protection. the ovp in function is explained in more detail in the applications information section.
www.vishay.com 8 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 applications information powering sip11203/sip11204 the sip11203/sip11204 has an internal pre-regulator to provide 5 v at v l , which biases many of the internal sub-circuits. this allows the ic to operate from any input voltage within the allowable v in range. at the same time, v in provides the supply voltage to the gate driver outputs (outa and outb) directly. the gate drive level to the synchr onous rectifier mosfets is determined by v in the v in voltage can be derived using conventional methods, such as an extra winding on the power trans- former or on the output inductor. alternatively, this sup- ply can be derived from the pulse transformer used to transmit synchronous rectifie r timing signals from the primary to the secondary, as shown in figure 2 below. the voltage level on v in will be determined by the turn ratio of the pulse transformer and the differential volt- age between srl of the si9122, si9122a, si9122e and srh of of the si9122, si9122a, si9122e. note that this circuit will cause th e voltages at ina and inb to be twice that of v in . therefore it may be necessary to limit the voltage seen by ina and inb in order to avoid exceeding their recommended operating values. start-up driver operation during start-up of the sip11203/sip11204, the mos- fet drivers (outa and outb) are disabled until v l is at 90 % of its final value. to fully prevent any spurious turn-on of the synchronous rectifier mosfets, the gates of the mosfets are held off during this start up period. until the main drivers are enabled, the ina and inb drive paths are re-routed, or ?swapped,? inside the ic. in conjunction with a dedicated n-channel hold-off mosfet ?inverter? placed in parallel with each main driver, this allows the ic to ground the appropriate syn- chronous rectifier gate at the necessary time. see fig- ure 3. if the first two pulses comi ng through the pulse trans- former are considered, the following sequence of events follows: ? ina goes low, which would normally command the outa driver to go low. this would prevent spurious turn-on of the associated synchronous rectifier. however, since the voltage to the ic is below its normal operating level, it cannot be guaranteed that outa can in fact go to it s necessary state. for this reason, the outa and outb drivers are disabled while v l < uvlo r . ? w hen ina goes low, inb will be driven to a level of 2 x v in . this is due to the way in which the second- ary of the pulse transformer is rectified to provide v in . specifically, this resu lts from the rectifier diodes clamping the secondary?s negative excur- sions one diode drop below ground (see figure 2). figure 2. typical schematic showing how the v in supply for sip11203/sip11204 is generated using the pulse transformer providing the synchronous rectifier timing signals srh srl i n a v i n b g n d i n sip11203 sip11204 srh srl i n a v i n b g n d i n sip11203 sip11204 sip11203 sip11204
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 9 vishay siliconix sip11203/sip11204 ? w hile v l is below the uvlo r threshold, the ic ?swaps? the synchronous rectifier drive paths. this causes the high-going signal on inb to be applied to the gate of an n-channel hold-off mosfet, which is in parallel with t he main outa driver. this mosfet inverts the signal from inb, which causes its drain to be pulled towards ground. this holds outa low. ? during the deadtime in wh ich neither inb nor ina is driven high, the voltage on ina and that on inb will be equal to the voltage on v in . depending upon the exact value of v in , this may or may not result in both outa and outb being pulled low by their associated inverter mosfets. ? during the next cycle of converter operation, all of the above applies with the exception that inb is now driven low, which will cause ina to be driven high. this will in turn caus e the hold-off mosfet in parallel with the main outb driver to conduct, thereby holding outb low. in this way, the sip11203/sip11204 ?swap and invert? function prevents any unwanted turn-on of the syn- chronous rectifiers during start-up. once v l reaches 90 % of its final value, the dr ive path inside the ic is no longer swapped, and the inverting hold-off mosfets are disabled. functional block diagram start-up driver operation assuming that v in rises with suitable rapidity to a volt- age greater than 5.5 v, the factors controlling the rate of rise of v l are the external v l bypass capacitor value and the pre-regulator?s curren t limit. this gives the fol- lowing two equations: ? the time from start-up to cuvlo r ? (4.45 v/35 ma) x c vl , and ? the time from start-up to uvlo r ? (4.45 v/35 ma) x c vl . once v l has reached 90 % of its final value, the clamp holding v ref at 0 v is released, allowing the voltage on the v ref pin to rise at a rate set by the value of the v ref capacitor. this gives the following equation : ? the time from uvlo r to v ref attaining a voltage of 1.1 v ? (1.1 v/410 a) x c vref . these relationships are shown in figure 4. figure 3. during converter startup, the synchronous mosfet gate-driver outputs of the sip11203/sip11204 are reversed and invert ed to prevent spurious mosfet switching hold-off mosfet hold-off mosfet sw1 and sw2 are closed at start- u p. sw1 and sw2 open w hen v l > u v lo r . sw1 sw2
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 10 vishay siliconix sip11203/sip11204 normal driver operation in normal operation, outa responds to ina, and outb to inb. the signal path from input to output is non-inverting . the output drivers have high and delib- erately asymmetrical curren t sink and source capabili- ties (4 a i sink , 2.2 a i source ). the high currents allow driving large synchronous re ctifiers at the switching frequencies found in modern power converters. at the same time, the driver asymmetry enforces a rapid turn- off of the rectifier mosfets relative to their turn-on, to avoid rectifier crossconduction, and the low driver im- pedances to pgnd help ensure that the rectifier mos- fets do not exhibit unwanted turn-on during converter operation. as with most logic circuits, outa and outb do not ex- hibit indeterminate output states even the transitions at ina and inb are excessively slow. the solid and sharp driving signals from outa and outb will ensure the proper function of the rectifier mosfets in the final application circuit. power-down driver operation if the timing pulses from the primary of the dc-dc con- verter cease, the sip11203/sip11204 must assume that the power to the primary of the dc-dc converter has failed. upon detecting this condition, the part must put the main synchronous rectifier drivers into a ?safe? condition, and simultaneously ensure that the rectifier mosfets are turned off. a unique feature of the sip11203/sip11204 is their ability to turn off the syn- chronous rectifiers via a controlled excursion through their linear region. this can help to prevent output ring- ing at turn-off. a missing-pulses detector is provided on the ic to ini- tiate the soft power down. this detector, which is en- abled once the v ref pin has reached 1.1 v, continually monitors ina and inb for lack of switching activity. an external resistor from r pd to ground defines a current out of c pd (i = 2.5 v/r pd ), which is used to charge an external capacitor from c pd to ground. the voltage on c pd is internally compared to the 2.5 v developed by v refint . w henever either input goes low, the voltage at c pd is reset to 0 v. however, if both inputs are high for a period of r pd c pd , the voltage at c pd will ex- ceed the 2.5 v comparison threshold, and the power- down latch will be set (see figure 6). ?the v ref pin bypass capacitor is discharged towards 0 v, to ensure an orderly soft-start cycle when operation resumes, ? the main drivers are forced into a high-impedance state, ? internal pull-downs (current sinks) from the outa and outb pins to ground are enabled, ? the pull-down currents on outa and outb are set by r pd , to allow a ?soft? turn-off of the synchronous rectifiers. figure 4. soft-start parameters of the sip11203/si p11204 are programmable with external components v v l v ref 0.9* v l 3.55 v time 1.225 v 5 v internal logic circ u its ena b led v ref released to rise rate of rise determined b y external v ref capacitor rate of rise determined b y external v l capacitor 2.5 v v refi n t ena b led b y cu v lo r
www.vishay.com 11 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 power-down driver operation (cont?d) the internal pull-downs ensure that the synchronous rectifiers are in the off state before the bias supply to the ic has collapsed (see figure 5). since these pull- downs have a lower current-s inking capab ility than the main outa and outb drivers, they can cause the rec- tifier mosfets to transition from full conduction to the off state via their linear region of operation. this soft turn-off allows the use of the gradually increasing rec- tifier channel impedances to help damp lc oscillations that might otherwise occur at the converter's output. the gate pull-down current value, and therefore the in- terval during which the rect ifier mosfets are in tran- sition from fully on to fully off, is programmed by the resistor from rpd to ground. this current is given by i pull-do w n = 200* v refint /r pd . this programma- bility allows the choice of a gate discharge time which best accommodates the design variables of l out , c out , and synchronous rectif ier mosfet characteris- tics. the power-down latch will be reset, and a soft-start cy- cle will occur, when the logica l and of two conditions is true: ? the voltage on the v ref capacitor is 20 % (245 mv) of its nominal 1.225 v, and ? the exclusive-or of ina and inb is true, that is, one input is in low while the other is high. note that low values of r pd will increase the main sup- ply current. it is recommended that r pd be kept 15 k to prevent excessive power dissipation. synchronous rectifier phase-in and rising edge delay the sip11203/sip112 04 has the ability to ?phase in? the synchronous rectifiers at start-up. this causes the rectifier mosfets to initia lly be used as conventional pn (or schottky) diodes, then as synchronous rectifi- ers for an increasing percentage of each switching cy- cle, until finally they are operating completely as synchronous switches. w hen this feature of the ic is used, the resistance r del , which is connected be- tween the r del pin and ground, determines the time required for the transition from diode-mode operation to fully synchronous rectification. to achieve this phase-in of the synchronous rectifiers, an internally extended propagation delay ( t del ) is in- troduced between the rising edge of each input (ina or inb) and the rising edge of the corresponding output (outa or outb). the length of this delay is propor- tional to r del and inversely proportional to v ref : t del ? (1.5 ns x r del x 1.225 v)/(1 k x v ref ). therefore t del decreases throughout the interval during which v ref is rising (i.e., during the time follow- ing converter start-up or a sip11203/sip11204 soft- start event). w hen the phase-in period has ended, the final high-going propagation delay is t del(final) = t pdr + t del(final) = t pdr + [(1.5 ns x r del )/1 k ) ], as shown in the typical curves. figure 5. the shutdown sequence of sip11203/sip11204 prevents the synchronous mosfet of a half-bridge converter from discharging a prebiased output when supplied power is removed i n a/b outa/b c pd v ref 2.5 v v i n v l restart shutdow figure 6. power down detect and ?soft? turn-off
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 12 vishay siliconix sip11203/sip11204 synchronous rectifier phase-in and rising edge delay (cont?d) the three modes of operation experienced during syn- chronous rectifier phase-in are, in order : ? some number of converter switching cycles may occur during which t del 2/f converter . during this interval, the synchronous rectifiers are held off for a long enough time that they will act as conven ional diodes only. this in terval of operation will be some portion of the time it takes for the voltage on the v ref pin to climb to its final 1.225 v value. ? some number of conv erter switching cycles will occur during which 2/f converter > t del > t del(final) . during this interval, the synchronous rectifiers are held off for a portion of their possible conduction interval, with that percentage decreas- ing in a 1/x fashion from 100 % of their possible conduction time to a percentage set by r del and f converter . this interval of operation will be the remainder of the time it takes for the voltage on the v ref pin to climb to its final 1.225 v value. ? w hen v ref is equal to 1.225 v, normal converter operation occurs, with the synchronous rectifiers being held off for a time t del(final) . this final delay time can be made equal to the inherent propagation delay of the ic?s output drivers, as described below. the synchronous rectifier phase-in is diagrammed in figure 7. connecting r del to v l will completely disable the syn- chronous rectifier phase-in circuitry. the rectifier mos- fets will then transition di rectly from diode-mode full synchronous rectifier operation when the ic?s v l sup- ply exceeds the uvlo r threshold. the residual rising- edge delay otherwise introduced by r del will also be set to zero. (note: by examination of the above equa- tions, grounding the r del pin could be another means of setting t del to zero. doing so is not recommended in practice as this will cause unnecessary power dissi- pation in the ic: the suppl y current will increase by 0.15 ma if r del is connected to v l , but by 0.5 ma if this pin is shorted to ground. also, due to the internal circuitry of the ics, the propagation delay time is reduced by several nanoseconds when the r del pin is connected to v l as opposed to when it is grounded.) in some applications it is desirable to make use of the rectifier phase-in feature while eliminating the residual t del . to achieve this, the appropriate resistance should be connected from the r del pin to ground, and the r del pin should be pulled up to v l using a suitable op-amp or comparator, such as the lmv321m7, once the output voltage of the converter approaches its final value. in such a circuit, v cc for the op-amp or compar- ator should be obtained from v l of the sip11203/ sip11204. the phase-in of synchronous rectification helps to pre- vent disturbances in the output voltage at start-up, which could occur due to the differential in output volt- age drop which occurs when the rectifier mosfets make an abrupt transition from operation as diodes to operation as synchronous rectifiers. the figure 8 below shows how the rising edge delay is implemented in conjunction with the si9122 and allows the effective bbm2 and bbm4 falling delays to be modified independently of rising delays bbm1 and bbm3. for definition of the bbm delays please see the si9122 datasheet . figure 7. the sip11203/sip11204 gate-drive output signals are delayed during phase-in prevent disturbing the output voltage time i n b out b i n a out a rising edge delay red u ces d u ring phase-in. phase-in period set r del i n b out b i n a out a rising edge delay d u ring normal operation. period set b y r del ( n ote: can b e set to zero) phase-in finished phase-in period
www.vishay.com 13 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 output over-voltage protection the sip11203/sip11204 provide output over-voltage protection (ovp) by means of a dedicated internal comparator. one input of the ovp comparator is brought out to the ovp in pin, and the other is returned to an internal reference voltage that is fixed at 120 % of the 1.225 v v ref value, or 1.47 v. a voltage in ex- cess of 1.47 v at the ovp in pin indicates an ovp fault. the ovp circuitry operates in two different ways, de- pending upon whether the sip11203/sip11204 is in start-up mode, or in normal operation. in this context, start-up mode is defined as device operation during that period for which v ref is less than 90 % of its 1.225 v value, or 1.1 v . start-up mode: if the 1.47 v ovp threshold is exceeded during start- up, the driver outputs outa and outb are held low until the voltage on the v ref pin has exceeded 1.1 v. the driver outputs are then released to respond to ina and inb. normal operation mode: if the ovp threshold is exceeded, or remains exceed- ed, after v ref has reached 1.1 v, the ovp latch will be set. this will cause the driver outputs to be forced high for sip11203, or forced low for sip11204. at the same time, an on-chip transistor will discharge the bypass capacitor at the v ref pin towards ground. the ovp latch is reset when the logical and of two conditions: ? the voltage on the v ref pin must be 20 % (245 mv) of its nominal 1.225 v level, to ensure an orderly soft-start cycle when operation resumes, and ? the voltage at the ovp in pin must be 1.1 v, indi- cating that the ovp fault has been cleared. w hen the ovp latch is reset, the sip11203/sip11204 will release their outputs, an d return to normal opera- tion via a soft-start cycle. to prevent spurious activation of the over-voltage func- tion, the over-voltage condition must be present for five switching instances, where a switching instance is de- fined as activity on either in a or in b . on the fifth switch- ing instance the overvoltage condition is latched. if the over voltage condition disappears the ic will not recog- nize an over-voltage as being present and the counter will be reset to zero. note that the ovp in threshold voltage is derived from the internal 2.5 v reference voltage v refint , which is derived from v in , and therefore is not delayed by the rise time of either v l or v ref . figure 8. the delay of sip11203 and sip11204 gate-drive outpu t signals compensate the break -before-make sw itching action discrepancies arising from propagation delays pwm pwm pwm pwm dl dl out a out a bbm1 bbm2 bbm3 bbm4 rising edge delay set b y r del
document number: 73868 s-pending?rev. a, 02-may-06 www.vishay.com 14 vishay siliconix sip11203/sip11204 typical characteristics v ref vs. temperature error amp v oh vs. i oh supply current without load vs. v in 1.16 1.1 8 1.2 1.22 1.24 1.26 1.2 8 - 50 0 50 100 150 temperat u re (c) v ref ( v ) v i n = 7.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 4 i oh (ma) v h o ) v ( 3 5 7 9 11 13 5 7 9 11 13 15 v i n ( v ) i n i (ma) f i n = 1 mhz f i n = 500 khz f i n = 250 khz v l vs. temperature error amp v ol vs. i ol 250 khz supply current vs. c l 4.75 4. 8 4. 8 5 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 - 50 0 50 100 150 temperat u re (c) v l ( v ) v = 7.5 v i n i l = 3 ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0 0.4 0. 8 1.2 1.6 i ol (ma) v ol ( v ) 3 8 13 1 8 23 2 8 5 7 9 11 13 v i n ( v ) i i n (ma) c l = 6 nf c l = 3 nf c l = 0 nf
www.vishay.com 15 document number: 73868 s-pending?rev. a, 02-may-06 vishay siliconix sip11203/sip11204 typical characteristics quiescent current vs. r del quiescent current vs. r pd r d(source) vs. temperature 3.5 3.6 3.7 3. 8 3.9 4 4.1 4.2 0 10 20 30 r del (k ) i (ma) q v i n = 7.5 v c pd = 10 nf 3 4 5 6 7 8 9 0 5 10 15 20 25 30 r pd (k ) i (ma) q v i n = 7.5 v c pd = 10 nf 1.2 1.6 2 2.4 2. 8 3.2 - 50 0 50 100 150 temperat u re (c) r d(source) ( ) v i n = 5.5 v v i n = 7.5 v v i n = 13 v rise delay vs. r del powerdown timeout vs. r pd r d(sink) vs. temperature 25 35 45 55 65 75 8 5 0 5 10 15 20 25 30 r del (k ) rise delay (ns) v in = 7.5 v 1.5 ns/ k 0 50 100 150 200 250 300 0 10 20 30 r pd (k ) r d p c / / d p (ns) 1 1.1 1.2 1.3 1.4 1.5 1.6 - 50 0 50 100 150 temperat u re (c) r d(si n k) ( ) v i n = 5.5 v v i n = 7.5 v v i n = 1.3 v
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.

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